1. Field of the Invention
The present invention relates to high power MOSFET transistors and, more particularly, to high power MOSFET transistors with low on-resistance employing a trench MOS gate structure.
2. Description of the Related Art
To optimize the power-handling capability of any power semiconductor device, it is essential to maximize the cell packing density. It has become evident both experimentally and analytically that device physics limitations are restricting further advances in cell packing density, and thus in MOSFET performance, using a surface channel formed by the self-aligned double-diffused process, commonly known as DMOS.
An improvement in cell packing density can be achieved by utilizing a trench MOS gate structure rather than a standard DMOS structure. The lack of JFET pinching effect in a trench gate structure also results in a significantly lower on-state resistance compared with a DMOS structure. Low on-resistance is particularly important when MOSFETs are used in low-frequency power electronic applications, such as automotive electronics.
A conventional trench power MOSFET is shown in FIG. 1. The device includes an N.sup.+ source region 2, a P base or channel region 4, an N.sup.- region 6 and an N.sup.+ region 8. A polysilicon gate 10 is formed in trenches on both sides of P base 4 and separated therefrom by a thin layer of oxide 11. A source electrode 12 on the upper surface of the device covers source region 2. A drain electrode 14 on the bottom surface of the device covers N.sup.+ region 8.
The operation of the device of FIG. 1 is as follows. With the drain electrode 14 positive with respect to the source electrode 12, current flows upward through the device when a positive potential is applied to gate 10. The positive potential on gate 10 inverts P base 4, forming an n-channel therethrough, permitting current to flow from drain to source.
While the trench power MOSFET of FIG. 1 has significant advantages over a DMOS transistor in terms of cell packing density, the inclusion of a P base in the structure undesirably contributes to on-resistance, because of channel resistance when the p-channel is inverted. This sets a limit on the amount that on-resistance can be reduced in a DMOS device. Additionally, the conventional trench power MOSFET shown in FIG. 1 has a parasitic P-N junction, which presents a problem during synchronous rectification.
An enhancement type of structure for a trench power MOSFET is shown in FIG. 2, wherein like elements are indicated by like reference numerals. This device, described by B. Baliga, "The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET," IEEE Electron Device Letters, Vol. 13, No. 8, August 1992, pp. 427-29), does not contain a P base region, and therefore has no P-N junction between the source and drain regions. Unlike the depletion type trench power MOSFET shown in FIG. 1, current conduction in the device of FIG. 2 occurs along the surface of an accumulation layer formed along the trench sidewalls, resulting in a much lower on-resistance. Additionally, in the device of FIG. 2, a drift region doping below 1.times.10.sup.14 cm.sup.-3 can be used, while an optimal drift region doping of 2.times.10.sup.16 cm.sup.-3 is required for the trench power MOSFET of FIG. 1. Further, the structure of FIG. 2 advantageously does not contain a parasitic P-N junction.
In order to turn off the device of FIG. 2, a potential is applied to gate 10 to invert the N.sup.- region 6. However, in the FIG. 2 device, the depletion width due to the MOS gate is limited by the formation of an inversion layer of holes in the N.sup.- drift region. This limits the forward blocking capability of the device.